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12-bit, 170 msps/210 msps/250 msps, 1.8 v analog-to-digital converter ad9230 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features snr = 64.9 dbfs @ f in up to 70 mhz @ 250 msps enob of 10.4 @ f in up to 70 mhz @ 250 msps (?1.0 dbfs) sfdr = ?79 dbc @ f in up to 70 mhz @ 250 msps (?1.0 dbfs) excellent linearity dnl = 0.3 lsb typical inl = 0.5 lsb typical lvds at 250 msps (ansi-644 levels) 700 mhz full power analog bandwidth on-chip reference, no external decoupling required integrated input buffer and track-and-hold low power dissipation 434 mw @ 250 mspslvds sdr mode 400 mw @ 250 mspslvds ddr mode programmable input voltage range 1.0 v to 1.5 v, 1.25 v nominal 1.8 v analog and digital supply operation selectable output data format (offset binary, twos complement, gray code) clock duty cycle stabilizer integrated data capture clock applications wireless and wired broadband communications cable reverse path communications test equipment radar and satellite subsystems power amplifier linearization functional block diagram agnd pwdn rbias avdd (1.8v) vin+ vin? cml track-and-hold reference adc 12-bit core output staging lvds clk+ clk? clock management serial port reset sclk sdio csb dco? dco+ or? or+ d11 to d0 drgnd drvdd 12 12 ad9230 06002-001 figure 1. functional block diagram general description the ad9230 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. the product operates at up to a 250 msps conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. all necessary functions, including a track-and-hold (t/h) and voltage reference, are included on the chip to provide a complete signal conversion solution. the adc requires a 1.8 v analog voltage supply and a differential clock for full performance operation. the digital outputs are lvds (ansi-644) compatible and support either twos complement, offset binary format, or gray code. a data clock output is available for proper output data timing. fabricated on an advanced cmos process, the ad9230 is available in a 56-lead lfcsp, specified over the industrial temperature range (?40c to +85c). product highlights 1. high performancemaintains 64.9 dbfs snr @ 250 msps with a 70 mhz input. 2. low powerconsumes only 434 mw @ 250 msps. 3. ease of uselvds output data and output clock signal allow interface to current fpga technology. the on-chip reference and sample and hold provide flexibility in system design. use of a single 1.8 v supply simplifies system power supply design. 4. serial port controlstandard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. 5. pin-compatible family10-bit pin-compatible family offered as ad9211.
ad9230 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications.......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 timing diagrams.......................................................................... 7 absolute maximum ratings............................................................ 8 thermal resistance ...................................................................... 8 esd caution.................................................................................. 8 pin configurations and function descriptions ........................... 9 equivalent circuits ......................................................................... 13 typical performance characteristics ........................................... 14 theory of operation ...................................................................... 21 analog input and voltage reference ....................................... 21 clock input considerations...................................................... 22 power dissipation and power-down mode ........................... 23 digital outputs ........................................................................... 23 timing ......................................................................................... 24 rbias........................................................................................... 24 ad9230 configuration using the spi ..................................... 24 hardware interface..................................................................... 25 configuration without the spi ................................................ 25 memory map .................................................................................. 27 reading the memory map table.............................................. 27 reserved locations .................................................................... 27 default values ............................................................................. 27 logic levels................................................................................. 27 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 2/07revision 0: initial version
ad9230 rev. 0 | page 3 of 32 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.25 v, dcs enabled, unless otherwise noted. table 1. ad9230-170 ad9230-210 ad9230-250 parameter 1 temp min typ max min typ max min typ max unit resolution 12 12 12 bits accuracy no missing codes full guaran teed guaranteed guaranteed offset error 25c 4.2 4.3 4.5 mv full ?12 12 ?12 12 ?12 12 mv gain error 25c 0.89 1.0 1.1 mv full ?1.5 3.5 ?1.5 3.5 ?1.5 3.5 % fs differential nonlinearity 25c 0.3 0.3 0.3 lsb (dnl) full ?0.5 0.5 ?0.5 0.5 ?0.6 0.6 lsb integral nonlinearity (inl) 25c 0.5 0.4 0.5 lsb full ?0.75 0.75 ?0.75 0.75 ?1.0 +1.0 lsb temperature drift offset error full 9 8 7 v/c gain error full 0.019 0.021 0.018 %/c analog inputs (vin+, vin?) differential input voltage range 2 full 0.98 1.25 1.5 0.98 1.25 1.5 0.98 1.25 1.5 v p-p input common-mode voltage full 1.4 1.4 1.4 v input resistance (differential) full 4.3 4.3 4.3 k input capacitance 25c 2 2 2 pf power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v supply currents i avdd 3 full 136 145 154 164 181 194 ma i drvdd 3 /sdr mode 4 full 58 61 59 62 60 63 ma i drvdd 3 /ddr mode 5 full 39 40 41 ma power dissipation 3 full mw sdr mode 4 full 349 371 383 407 434 463 mw ddr mode 5 full 315 349 400 mw 1 see the an-835 application note , understanding high speed adc testing and evaluation, for a complete set of definitions and how these tests were completed. 2 the input range is programmable through the spi, and the range specified reflects the nominal values of each setting. see the memory map section. 3 i avdd and i drvdd are measured with a ?1 dbfs, 10.3 mhz sine input at rated sample rate. 4 single data rate mode; this is the default mode of the ad9230. 5 double data rate mode; user-programmable feature. see the memory map section.
ad9230 rev. 0 | page 4 of 32 ac specifications 1 avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.25 v, dcs enabled, unless otherwise noted. table 2. ad9230-170 ad9230-210 ad9230-250 parameter 2 temp min typ max min typ max min typ max unit snr f in = 10 mhz 25c 63.8 64.6 63.7 64.5 63.3 64.1 db full 63.5 63.4 62.5 db f in = 70 mhz 25c 63.5 64.3 63.3 64.2 63.0 63.9 db full 63.3 63.1 62.3 db f in = 170 mhz 3 25c 63.5 63.4 63.3 db f in = 225 mhz 25c 63.0 61.5 63.3 db sinad f in = 10 mhz 25c 63.7 64.5 63.6 64.4 63.3 64.0 db full 63.4 63.4 62.4 db f in = 70 mhz 25c 63.3 64.1 63.2 64.0 62.9 63.7 db full 63.1 63.0 62.2 db f in = 170 mhz 3 25c 63.3 63.1 63.0 db f in = 225 mhz 25c 61.8 61.1 62.8 db effective number of bits (enob) f in = 10 mhz 25c 10.6 10.6 10.5 bits f in = 70 mhz 25c 10.5 10.5 10.4 bits f in = 170 mhz 3 25c 10.4 10.4 10.3 bits f in = 225 mhz 25c 10.1 10.0 10.3 bits worst harmonic (second or third) f in = 10 mhz 25c ?82 ?78 ?86 ?80 ?84 ?79 dbc full ?78 ?78 ?76 dbc f in = 70 mhz 25c ?78 ?76 ?80 ?77 ?79 ?76 dbc full ?75 ?75 ?75 dbc f in = 170 mhz 3 25c ?78 ?79 ?78 dbc f in = 225 mhz 25c ?68 ?70 ?75 dbc worst other (sfdr excluding second and third) f in = 10 mhz 25c ?89 ?84 ?89 ?84 ?84 ?79 dbc full ?83 ?83 ?76 dbc f in = 70 mhz 25c ?89 ?83 ?86 ?81 ?83 ?79 dbc full ?83 ?81 ?75 dbc f in = 170 mhz 3 25c ?89 ?79 ?83 dbc f in = 225 mhz 25c ?80 ?79 ?80 dbc two-tone imd 140.2 mhz/141.3 mhz @ ?7 dbfs 25c 73 75 78 dbc 170.2 mhz/171.3 mhz @ ?7 dbfs 25c 67 73 dbc analog input bandwidth 25c 700 700 700 mhz 1 all ac specifications tested by driving clk+ and clk? differentially. 2 see the an-835 application note , understanding high speed adc testing and evaluation, for a complete set of definitions and how these tests were completed. 3 140 mhz for the ad9230-170 speed grade, 170 mhz for the ad9230-210 and ad9230-250 speed grades.
ad9230 rev. 0 | page 5 of 32 digital specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.25 v, dcs enabled, unless otherwise noted. table 3. ad9230-170 ad9230-210 ad9230-250 parameter 1 temp min typ max min typ max min typ max unit clock inputs logic compliance full cmos/lvds/lvpec l cmos/lvds/lvpecl cmos/lvds/lvpecl internal common-mode bias full 1.2 1.2 1.2 v differential input voltage full 0.2 6 0.2 6 0.2 6 v p-p input voltage range full avdd ? 0.3 avdd + 1.6 avdd ? 0.3 avdd + 1.6 avdd ? 0.3 avdd + 1.6 v input common-mode range full 1.1 avdd 1.1 avdd 1.1 avdd v high level input voltage (v ih ) full 1.2 3.6 1.2 3.6 1.2 3.6 v low level input voltage (v il ) full 0 0.8 0 0.8 0 0.8 v high level input current (i ih ) full ?10 +10 ?10 +10 ?10 +10 a low level input current (i il ) full ?10 +10 ?10 +10 ?10 +10 a input resistance (differential) full 16 20 24 16 20 24 16 20 24 k input capacitance full 4 4 4 pf logic inputs logic 1 voltage full 0.8 vdd 0.8 vdd 0.8 vdd v logic 0 voltage full 0.2 avdd 0.2 avdd 0.2 avdd v logic 1 input current (sdio) full 0 0 0 a logic 0 input current (sdio) full ?60 ?60 ?60 a logic 1 input current (sclk, pdwn, csb, reset) full 55 55 50 a logic 0 input current (sclk, pdwn, csb, reset) full 0 0 0 a input capacitance 25c 4 4 4 pf logic outputs 2 v od differential output voltage full 247 454 247 454 247 454 mv v os output offset voltage full 1.125 1.375 1.125 1.375 1.125 1.375 v output coding twos complement, gray code, or offset binary (default) 1 see the an-835 application note , understanding high speed adc testing and evaluation, for a complete set of definitions and how these tests were completed. 2 lvds r termination = 100 .
ad9230 rev. 0 | page 6 of 32 switching specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.25 v, dcs enabled, unless otherwise noted. table 4. ad9230-170 ad9230-210 ad9230-250 parameter (conditions) temp min typ max min typ max unit maximum conversion rate full 170 210 250 msps minimum conversion rate full 40 40 40 msps clk+ pulse width high (t ch ) full 2.65 2.9 2.15 2.4 1.8 2.0 ns clk+ pulse width low (t cl ) full 2.65 2.9 2.15 2.4 1.8 2.0 ns output (lvds ? sdr mode) 1 data propagation delay (t pd ) full 3.0 3.0 3.0 ns rise time (t r ) (20% to 80%) 25c 0.2 0.2 0.2 ns fall time (t f ) (20% to 80%) 25c 0.2 0.2 0.2 ns dco propagation delay (t cpd ) full 3.9 3.9 3.9 ns data to dco skew (t skew ) full ?0.3 0.1 0.5 ?0.3 0.1 0.5 ?0.3 0.1 0.5 ns latency full 7 7 7 cycles output (lvds ? ddr mode) 2 data propagation delay (t pd ) full 3.8 3.8 3.8 ns rise time (t r ) (20% to 80%) 25c 0.2 0.2 0.2 ns fall time (t f ) (20% to 80%) 25c 0.2 0.2 0.2 ns dco propagation delay (t cpd ) full 3.9 3.9 3.9 ns data to dco skew (t skew ) full ?0.5 0.1 0.3 ?0.5 0.1 0.3 ?0.5 0.1 0.3 ns latency full 7 7 7 cycles aperture uncertainty (jitter, t j ) 25c 0.2 0.2 ps rms 1 see figure 2. 2 see figure 3.
ad9230 rev. 0 | page 7 of 32 timing diagrams n ? 1 n n + 2 n + 3 n + 4 n + 5 n + 1 clk+ n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 clk? dco+ dco? dx+ dx? vin t a t ch t cl 1/ f s t cpd t skew t pd 06002-002 figure 2. single data rate mode n ? 1 n n + 2 n + 3 n + 4 n + 5 n + 1 clk+ clk? dco+ dco? d6 n ? 8 d0 n ? 7 d6 n ? 7 d0 n ? 6 d6 n ? 6 d0 n ? 5 d6 n ? 5 d0 n ? 4 d6 n ? 4 d0 n ? 3 d0/d6+ d0/d6? d11 n ? 8 d5 n ? 7 d11 n ? 7 d5 n ? 6 d11 n ? 6 d5 n ? 5 d11 n ? 5 d5 n ? 4 d11 n ? 4 d5 n ? 3 d5/d11+ d5/d11? vin t a t ch t cl 1/ f s t cpd t skew t pd 06002-003 6 msbs 6 lsbs figure 3. double data rate mode
ad9230 rev. 0 | page 8 of 32 absolute maximum ratings table 5. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to drgnd ?0.3 v to +2.0 v agnd to drgnd ?0.3 v to +0.3 v avdd to drvdd ?2.0 v to +2.0 v d0+/d0? through d13+/d13? to drgnd ?0.3 v to drvdd + 0.3 v dco to drgnd ?0.3 v to drvdd + 0.3 v or to dgnd ?0.3 v to drvdd + 0.3 v clk+ to agnd ?0.3 v to +3.9 v clk? to agnd ?0.3 v to +3.9 v vin+ to agnd ?0.3 v to avdd + 0.2 v vin? to agnd ?0.3 v to avdd + 0.2 v sdio/dcs to dgnd ?0.3 v to drvdd + 0.3 v pdwn to agnd ?0.3 v to +3.9 v csb to agnd ?0.3 v to +3.9 v sclk/dfs to agnd ?0.3 v to +3.9 v environmental storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. table 6. package type ja jc unit 56-lead lfcsp (cp-48-3) 30.4 2.9 c/w typical ja and jc are specified for a 4-layer board in still air. airflow increases heat dissipation, effectively reducing ja . in addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the ja . esd caution
ad9230 rev. 0 | page 9 of 32 pin configurations and function descriptions pin 1 indicator 1 d3? 2 d3+ 3 d4? 4 d4+ 5 d5? 6 d5+ 7 drvdd 8 drgnd 9 d6? 10 d6+ 11 d7? 12 d7+ 13 d8? 14 d8+ 35 vin+ 36 vin? 37 avdd 38 avdd 39 avdd 40 cml 41 avdd 42 avdd 34 avdd 33 avdd 32 avdd 31 rbias 30 avdd 29 pwdn 1 5 d 9 ? 1 6 d 9 + 1 7 d 1 0 ? 1 9 ( m s b ) d 1 1 ? 2 1 o r ? 2 0 ( m s b ) d 1 1 + 2 2 o r + 2 3 d r g n d 2 4 d r v d d 2 5 s d i o / d c s 2 6 s c l k / d f s 2 7 c s b 2 8 r e s e t 1 8 d 1 0+ 4 5 c l k ? 4 6 a v d d 4 7 d r v d d 4 8 d r g n d 4 9 d c o ? 5 0 d c o + 5 1 d 0 ? ( l s b ) 5 2 d 0 + ( l s b ) 5 3 d 1 ? 5 4 d 1 + 4 4 c l k + 4 3 a v d d top view (not to scale) pin 0 (exposed paddle) = agnd ad9230 5 5 d 2 ? 5 6 d 2 + 06002-004 figure 4. single data rate mode table 7. single data rate mode pin function descriptions pin no. mnemonic description 30, 32 to 34, 37 to 39, 41 to 43, 46 avdd 1.8 v analog supply. 7, 24, 47 drvdd 1.8 v digital output supply. 0 agnd 1 analog ground. 8, 23, 48 drgnd 1 digital output ground. 35 vin+ analog inputtrue. 36 vin? analog inputcomplement. 40 cml common-mode output pin. enabled through the sp i, this pin provides a reference for the optimized internal bias voltage for vin+/vin?. 44 clk+ clock inputtrue. 45 clk? clock inputcomplement. 31 rbias set pin for chip bias current. (place 1% 10 k resistor terminated to ground.) nominally 0.5 v. 28 reset cmos-compatible chip reset (active low). 25 sdio/dcs serial port interface (spi?) data input/output (s erial port mode); duty cycle stabilizer select (external pin mode). 26 sclk/dfs serial port interface clock (serial port mode); data format select pin (external pin mode). 27 csb serial port chip select (active low). 29 pwdn chip power-down. 49 dco? data clock outputcomplement. 50 dco+ data clock outputtrue. 51 d0? d0 complement output bit (lsb). 52 d0+ d0 true output bit (lsb). 53 d1? d1 complement output bit. 54 d1+ d1 true output bit. 55 d2? d2 complement output bit. 56 d2+ d2 true output bit. 1 d3? d3 complement output bit. 2 d3+ d3 true output bit. 3 d4? d4 complement output bit. 4 d4+ d4 true output bit.
ad9230 rev. 0 | page 10 of 32 pin no. mnemonic description 5 d5? d5 complement output bit. 6 d5+ d5 true output bit. 9 d6? d6 complement output bit. 10 d6+ d6 true output bit. 11 d7? d7 complement output bit. 12 d7+ d7 true output bit. 13 d8? d8 complement output bit. 14 d8+ d8 true output bit. 15 d9? d9 complement output bit. 16 d9+ d9 true output bit. 17 d10? d10 complement output bit. 18 d10+ d10 true output bit. 19 d11? d11 complement output bit (msb). 20 d11+ d11 true output bit (msb). 21 or? overrange complement output bit. 22 or+ overrange true output bit. 1 agnd and drgnd should be tied to a common quiet ground plane.
ad9230 rev. 0 | page 11 of 32 dnc = do not connect pin 1 indicator 1 d3/d9? 2 d3/d9+ 3 d4/d10? 4 d4/d10+ 5 (msb) d5/d11? 6 (msb) d5/d11 + 7 drvdd 8 drgnd 9 or? 10 or+ 11 dnc 12 dnc 13 dnc 14 dnc 35 vin+ 36 vin? 37 avdd 38 avdd 39 avdd 40 cml 41 avdd 42 avdd 34 avdd 33 avdd 32 avdd 31 rbias 30 avdd 29 pwdn 1 5 d n c 1 6 d n c 1 7 d n c 1 9 d n c 2 1 d n c / ( o r ? ) 2 0 d n c 2 2 d n c / ( o r + ) 2 3 d r g n d 2 4 d r v d d 2 5 s d i o / d c s 2 6 s c l k / d f s 2 7 c s b 2 8 r e s e t 1 8 d n c 4 5 c l k ? 4 6 a v d d 4 7 d r v d d 4 8 d r g n d 4 9 d c o ? 5 0 d c o + 5 1 d 0 / d 6 ? ( l s b ) 5 2 d 0 / d 6 + ( l s b ) 5 3 d 1 / d 7 ? 5 4 d 1 / d 7 + 4 4 c l k + 4 3 a v d d top view (not to scale) pin 0 (exposed p addle) = agnd ad9230 5 5 d 2 / d 8 ? 5 6 d 2 / d 8 + 06002-005 figure 5. double data rate table 8. double data rate mode pin function descriptions pin no. mnemonic description 30, 32 to 34, 37 to 39, 41 to 43, 46 avdd 1.8 v analog supply. 7, 24, 47 drvdd 1.8 v digital output supply. 0 agnd 1 analog ground. 8, 23, 48 drgnd 1 digital output ground. 35 vin+ analog inputtrue. 36 vin? analog inputcomplement. 40 cml common-mode output pin. enabled through the sp i, this pin provides a reference for the optimized internal bias voltage for vin+/vin?. 44 clk+ clock inputtrue. 45 clk? clock inputcomplement. 31 rbias set pin for chip bias current. (place 1% 10 k resistor terminated to ground.) nominally 0.5 v. 28 reset cmos-compatible chip reset (active low). 25 sdio/dcs serial port interface (spi) data input/output (ser ial port mode); duty cycle stabilizer select (external pin mode). 26 sclk/dfs serial port interface clock (serial port mo de); data format select pin (external pin mode). 27 csb serial port chip select (active low). 29 pwdn chip power-down. 49 dco? data clock outputcomplement. 50 dco+ data clock outputtrue. 51 d0/d6? d0/d6 complement output bit (lsb). 52 d0/d6+ d0/d6 true output bit (lsb). 53 d1/d7? d1/d7 complement output bit. 54 d1/d7+ d1/d7 true output bit. 55 d2/d8? d2/d8 complement output bit. 56 d2/d8+ d2/d8 true output bit. 1 d3/d9? d3/d9 complement output bit. 2 d3/d9+ d3/d9 true output bit. 3 d4/d10? d4/d10 complement output bit. 4 d4/d10+ d4/d10 true output bit. 5 d5/d11? d5/d11 complement output bit (msb). 6 d5/d11+ d5/d11 true output bit (msb).
ad9230 rev. 0 | page 12 of 32 pin no. mnemonic description 9 or? d6 complement output bit. (this pin is disabled if pin 21 is reconfigured through the spi to be or?.) 10 or+ d6 true output bit. (this pin is disabled if pin 22 is reconfigured through the spi to be or+.) 11 to 20 dnc do not connect. 21 dnc/(or?) do not connect. (this pin can be reconfigured as the overrange complement output bit through the serial port register.) 22 dnc/(or+) do not connect. (this pin can be reconfigured as the overrange true output bit through the serial port register.) 1 agnd and drgnd should be tied to a common quiet ground plane.
ad9230 rev. 0 | page 13 of 32 equivalent circuits 06002-006 1.2v 10k? 10k ? clk+ clk ? avdd figure 6. clock inputs v in+ avdd buf vin? avdd buf 2k? 2k? buf avdd v cml ~1.4v 0 6002-007 figure 7. analog inputs (v cml = ~1.4 v) sclk/dfs reset pdwn 1k ? 30k ? 06002-008 figure 8. equivalent sclk/dfs, reset, pdwn input circuit 06002-010 c sb 1k ? 26k ? avdd figure 9. equivalent csb input circuit drvdd dataout+ v? v+ dataout? v+ v? 0 6002-009 figure 10. lvds outputs (dx+, dx?, or+, or?, dco+, dco?) 06002-011 sdio/dcs 1k ? drvdd figure 11. equivalent sdio/dcs input circuit
ad9230 rev. 0 | page 14 of 32 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, rated sample rate, dcs enabled, t a = 25c, 1.25 v p-p differential input, ain = ?1 dbfs, unless otherwise noted. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 170msps 10.3mhz @ ?1.0dbfs snr: 64.6db enob: 10.6 bits sfdr: 82dbc 08 0 60 70 5040302010 06002-133 60 70 5040302010 amplitude (dbfs) frequency (mhz) figure 12. ad9230-170 64k point single-tone fft; 170 msps, 10.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 08 0 40000 35000 30000 25000 20000 15000 10000 5000 0 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 more number of hits bin input referred noise: 0.72 lsbs 06002-106 170msps 70.3mhz @ ?1.0dbfs snr: 64.3db enob: 10.5 bits sfdr: 78dbc 06002-134 70605040302010 amplitude (dbfs) frequency (mhz) figure 13. ad9230-170 64k point single-tone fft; 170 msps, 70.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 08 0 06002-014 170msps 140.3mhz @ ?1.0dbfs snr: 63.5db enob: 10.2 bits sfdr: 78dbc figure 14. ad9230-170 64k point single-tone fft; 170 msps, 140.3 mhz figure 15. ad9230-170 grounded input histogram; 170 msps 85 80 75 70 65 60 55 50 0 450 350 400 300250200 150 50 100 snr/sfdr (db) analog input frequency (mhz) snr (db) ?40c sfdr (dbc) ?40c snr (db) +25c sfdr (dbc) +25c sfdr (dbc) +85c snr (db) +85c 06002-109 figure 16. ad9230-170 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 1.25 v p-p full scale; 170 msps 100 10 20 30 40 50 60 70 80 90 0 90 0 20 10 30405060 80 70 snr/sfdr (db) amplitude (?dbfs) snr (dbfs) sfdr (dbc) sfdr (dbfs) snr (db) 06002-108 figure 17. ad9230-170 snr/sfdr vs. input amplitude; 140.3 mhz
ad9230 rev. 0 | page 15 of 32 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 ?1 4095 3071 2047 1023 inl (lsbs) output code 06002-018 figure 18. ad9230-170 inl; 170 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 08 0 70605040302010 amplitude (db) frequency (mhz) 06002-104 figure 19. ad9230-170 64k point, two-tone fft; 170 msps, 140.1 mhz, 141.1 mhz 140 60 70 80 90 100 110 120 130 50 380 310 320 340 330 350 360 370 300 40 180 160 140 120 100 80 60 current (ma) power (mw) sample rate (mhz) iavdd idvdd total power 06002-107 figure 20. ad9230-170 power supply current vs. sample rate 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?1 4095 3071 2047 1023 dnl (lsbs) output code 06002-021 figure 21. ad9230-170 dnl; 170 msps 120 0 20 40 60 80 100 ?90 0?10?20?30 ?40?50 ?60?70?80 sfdr (db) amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) 06002-111 figure 22. ad9230-170 two-tone sfdr vs. input amplitude; 170 msps, 140.1 mhz, 141.1 mhz
ad9230 rev. 0 | page 16 of 32 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 100 80 60 40 20 amplitude (dbfs) frequency (mhz) 06002-023 210msps 10.3mhz @ ?1.0dbfs snr: 64.5db enob: 10.5 bits sfdr: 79dbc figure 23. ad9230-210 64k point single-tone fft; 210 msps, 10.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 100 80 60 40 20 amplitude (dbfs) frequency (mhz) 06002-024 210msps 70.3mhz @ ?1.0dbfs snr: 63.9db enob: 10.4 bits sfdr: 80dbc figure 24. ad9230-210 64k point single-tone fft; 210 msps, 70.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 100 80 60 40 20 amplitude (dbfs) frequency (mhz) 06002-024 210msps 170.3mhz @ ?1.0dbfs snr: 631.7db enob: 9.9 bits sfdr: 67dbc figure 25. ad9230-210 64k point single-tone fft; 210 msps, 170.3 mhz 40000 35000 30000 25000 20000 15000 10000 5000 0 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 more number of hits bin input referred noise: 0.70 lsbs 06002-115 figure 26. ad9230-210 grounded input histogram; 210 msps 90 85 80 75 70 65 60 55 50 0 45040035030025020015010050 snr/sfdr (db) analog input frequency (mhz) snr (db) ?40c sfdr (dbc) ?40c snr (db) +25c sfdr (dbc) +25c snr (db) +85c sfdr (dbc) +85c 06002-118 figure 27. ad9230-210 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 1.25 v p-p full scale; 210 msps 100 90 80 70 60 50 40 30 20 10 0 90 0 1020304050607080 snr/sfdr (db) amplitude (?dbfs) snr (dbfs) sfdr (dbc) sfdr (dbfs) snr (db) 06002-117 figure 28. ad9230-210 snr/sfdr vs. input amplitude; 210 msps, 170.3 mhz
ad9230 rev. 0 | page 17 of 32 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 ?1 4095 3071 2047 1023 inl (lsbs) output code 06002-029 figure 29. ad9230-210 inl; 210 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 100 80 60 40 20 amplitude (db) frequency (mhz) 06002-112 figure 30. ad9230-210 64 point, two-tone fft; 210 msps, 170.1 mhz, 171.1 mhz 170 150 70 90 110 130 50 400 320 330 340 350 360 370 380 390 40 240 190 140 90 current (ma) power (mw) sample rate (msps) iavdd idrvdd total power 06002-116 figure 31. ad9230-210 power supply current vs. sample rate 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?1 4095 3071 2047 1023 dnl (lsbs) output code 06002-032 figure 32. ad9230-210 dnl; 210 msps 120 0 20 40 60 80 100 ?90 0?10?20?30 ?40?50 ?60?70?80 sfdr (db) amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) 06002-111 figure 33. ad9230-210 two-tone sfdr vs. input amplitude; 210 msps, 170.1 mhz, 171.1 mhz
ad9230 rev. 0 | page 18 of 32 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 120 100 80 60 40 20 amplitude (dbfs) frequency (mhz) 250msps 10.3mhz @ ?1.0dbfs snr: 64.1db enob: 10.5 bits sfdr: 84dbc 06002-123 figure 34. ad9230-250 64k point single-tone fft; 250 msps, 10.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 120 100 80 60 40 20 amplitude (dbfs) frequency (mhz) 250msps 70.3mhz @ ?1.0dbfs snr: 63.9db enob: 10.5 bits sfdr: 79dbc 06002-124 figure 35. ad9230-250 64k point single-tone fft; 250 msps, 70.3 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 120 100 80 60 40 20 amplitude (dbfs) frequency (mhz) 250msps 170.3mhz @ ?1.0dbfs snr: 63.3db enob: 10.5 bits sfdr: 78dbc 06002-125 figure 36. ad9230-250 64k point single-tone fft; 250 msps, 170.3 mhz 40000 35000 30000 25000 20000 15000 10000 5000 0 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 more number of hits bin input referred noise: 0.71 lsbs 06002-126 figure 37. ad9230-250 grounded input histogram; 250 msps 90 85 80 75 70 65 60 55 50 0 45040035030025020015010050 snr/sfdr (db) analog input frequency (mhz) snr (db) ?40c sfdr (dbc) ?40c snr (db) +25c sfdr (dbc) +25c snr (db) +85c sfdr (dbc) +85c 06002-118 figure 38. ad9230-250 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 1.25 v p-p full scale; 250 msps 100 10 20 30 40 50 60 70 80 90 0 100 90 0 20 10 304050 60 80 70 snr/sfdr (db) amplitude (?dbfs) snr (dbfs) sfdr (dbc) sfdr (dbfs) snr (dbc) 06002-128 figure 39. ad9230-250 snr/sfdr vs. input amplitude; 250 msps, 170.3 mhz
ad9230 rev. 0 | page 19 of 32 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 ?1 4095 3071 2047 1023 inl (lsbs) output code 06002-135 figure 40. ad9230-250 inl; 250 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 08 0 70605040302010 amplitude (db) frequency (mhz) 06002-121 figure 41. ad9230-250 64k point, two-tone fft; 250 msps, 170.1 mhz, 171.1 mhz 210 50 70 90 110 130 150 170 190 480 300 320 340 360 380 400 420 440 460 50 300 250 200 150 100 current (ma) power (mw) sample rate (msps) iavdd idrvdd total power 06002-127 figure 42. ad9230 power supply current vs. sample rate 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?1 4095 3071 2047 1023 dnl (lsbs) output code 06002-043 figure 43. ad9230-250 dnl; 250 msps 120 100 80 60 40 20 0 ?90 0?10?20?30?40?50?60?70 ?80 sfdr (db) amplitude (?dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) 06002-120 figure 44. ad9230-250 two-tone sfdr vs. input amplitude; 250 msps, 170.1 mhz, 171.1 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 0 30.72 61.44 92.16 122.88 amplitude (dbfs) frequency (mhz) 06002-101 figure 45. ad9230-250 64k point fft; four w-cdma carriers, if = 184 mhz, 245.6 msps
ad9230 rev. 0 | page 20 of 32 85 80 75 70 65 60 55 50 1.01.11.21.31.41.51.61.71.8 snr/sfdr (db) v cm (v) snr (db) sfdr (dbc) 06002-130 figure 46. snr/sfdr vs. common-mode voltage; 250 msps, 70.3 mhz @ ?1 dbfs 80 40 45 50 55 60 65 70 75 50 300 250 200 150 100 snr/sfdr (db) sample rate (msps) snr (db) sfdr (dbc) 06002-122 figure 47. snr/sfdr vs. sample rate; 250 msps, 170.3 mhz @ ?1 dbfs 85 80 75 70 65 60 0.9 1.6 1.5 1.4 1.3 1.2 1.1 1.0 snr/sfdr (db) analog input range (mhz) snr (dbfs) sfdr (dbfs) 06002-131 figure 48. snr/sfdr vs. analog input range; 250 msps, 170.3 mhz @ ?1 dbfs 90 20 30 40 50 60 70 80 0 102030405060708090100 snr/sfdr (db) input clock duty cycle (% clk+ high) snr (dbfs) w/ dcs on sfdr (dbfs) w/ dcs on snr (dbfs) w/ dcs off sfdr (dbfs) w/ dcs off 06002-100 figure 49. snr/sfdr vs. sample clock duty cycle; 250 msps, 170.3 mhz @ ?1 dbfs 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?60 120100 80 604020 0 ?20?40 gain (%fs) temperature (c) ad9230-210 ad9230-250 ad9230-170 06002-102 figure 50. gain vs. temperature 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 ?40 ?30 ?20 ?10 0 9080706050 40302010 offset (mv) temperature (c) ad9230-170 ad9230-210 ad9230-250 06002-103 figure 51. offset vs. temperature
ad9230 rev. 0 | page 21 of 32 theory of operation the ad9230 architecture consists of a front-end sample and hold amplifier (sha) followed by a pipelined switched capacitor adc. the quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sha that can be ac- or dc-coupled in differential or single-ended mode. the output- staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down, the output buffers go into a high impedance state. analog input and voltage reference the analog input to the ad9230 is a differential buffer. for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common-mode settling errors are symmetrical. the analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. snr and sinad performance degrades significantly if the analog input is driven with a single-ended signal. a wideband transformer, such as mini-circuits? adt1-1wt, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.3 v. an internal differential voltage reference creates positive and negative reference voltages that define the 1.25 v p-p fixed span of the adc core. this internal voltage reference can be adjusted by means of spi control. see the ad9230 configuration using the spi section for more details. differential input configurations optimum performance is achieved while driving the ad9230 in a differential input configuration. for baseband applications, the ad8138 differential driver provides excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is easily set to avdd/2 + 0.5 v, and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. vin+ vin? avdd cml ad8138 523 ? 499 ? 499? 499? 33 ? 33 ? 49.9 ? 1v p-p 0.1f 20pf ad9230 0 6002-055 figure 52. differential input configuration using the ad8138 at input frequencies in the second nyquist zone and above, the performance of most amplifiers may not be adequate to achieve the true performance of the ad9230. this is especially true in if undersampling applications where frequencies in the 70 mhz to 100 mhz range are being sampled. for these applications, differential transformer coupling is the recommended input configuration. the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few mhz, and excessive signal power can also cause core saturation, which leads to distortion. in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. vin+ vin? 15? 15? 50? 1.25v p-p 0.1f 2pf ad9230 06002-056 figure 53. differential transformer?coupled configuration as an alternative to using a transformer-coupled input at frequencies in the second nyquist zone, the ad8352 differential driver can be used (see figure 54 ). 06002-059 ad9230 ad8352 0 ? r 0 ? c d r d r g 0.1f 0.1f 0.1f vin+ vin? cml c 0.1f 0.1f 16 1 2 3 4 5 11 r 0.1f 0.1f 10 8, 13 14 v cc 200 ? 200 ? a nalog input a nalog input figure 54. differential input configuration using the ad8352
ad9230 rev. 0 | page 22 of 32 clock input considerations for optimum performance, the ad9230 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this signal is typically ac-coupled into the clk+ pin and clk? pin via a transformer or capacitors. these pins are biased internally and require no additional bias. figure 55 shows one preferred method for clocking the ad9230. the low jitter clock source is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the secondary transformer limit clock excursions into the ad9230 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9230 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 06002-060 0.1f 0.1f 0.1f 0.1f clock input 50? 100 ? clk? clk+ adc ad9230 mini-circuits adt1?1wt, 1:1z xfmr schottky diodes: hsm2812 figure 55. transformer-coupled differential clock if a low jitter clock is available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 56 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers offers excellent jitter performance. 06002-061 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 50 ? 1 50 ? 1 clk clk 1 50 ? resistors are optional. clk? clk+ adc ad9230 pecl driver clock input clock input figure 56. differential pecl sample clock 06002-070 clock input clock input 100 ? 0.1f 0.1f 0.1f 0.1f 50? 1 lvds driver 50? 1 clk clk 1 50 ? resistors are optional. clk? clk+ adc ad9230 ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 figure 57. differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applications, clk+ should be directly driven from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 58 ). although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages up to 3.3 v, making the selection of the drive logic voltage very flexible. 06002-071 0.1f 0.1f 0.1f 39k ? cmos driver 50? 1 optional 100? 0.1f clk clk 1 50? resistor is optional. clk? clk+ adc ad9230 a d9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 clock input figure 58. single-ended 1.8 v cmos sample clock 06002-072 0.1f 0.1f 0.1f cmos driver clk clk 1 50 ? resistor is optional. 0.1f clk? clk+ a d9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 adc ad9230 clock input 50 ? 1 optional 100? figure 59. single-ended 3.3 v cmos sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9230 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9230. when the dcs is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. however, some applications may require the dcs function to be off. if so, keep in mind that the dynamic range performance can be affected when operated in this mode. see the ad9230 configuration using the spi section for more details on using this feature. the duty cycle stabilizer uses a delay-locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately eight clock cycles to allow the dll to acquire and lock to the new rate.
ad9230 rev. 0 | page 23 of 32 clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated by snr degradation = 20 log 10 [1/2 f a t j ] in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 60 ). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9230. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs (visit www.analog.com ). 06002-065 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps analog input frequency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) figure 60. ideal snr vs. input frequency and jitter power dissipation an d power-down mode as shown in figure 42 , the power dissipated by the ad9230 is proportional to its sample rate. the digital power dissipation does not vary much because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. by asserting pdwn (pin 29) high, the ad9230 is placed in standby mode or full power-down mode, as determined by the contents of serial port register 08. reasserting the pdwn pin low returns the ad9230 into its normal operational mode. an additional standby mode is supported by means of varying the clock input. when the clock rate falls below 20 mhz, the ad9230 assumes a standby state. in this case, the biasing network and internal reference remain on, but digital circuitry is powered down. upon reactivating the clock, the ad9230 resumes normal operation after allowing for the pipeline latency. digital outputs digital outputs and timing the ad9230 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option similar to the ieee 1596.3 standard using the spi. this lvds standard can further reduce the overall power dissipation of the device, which reduces the power by ~39 mw. see the memory map section for more information. the lvds driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. the ad9230 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. no far-end receiver termination and poor differential trace routing may result in timing errors. it is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. an example of the lvds output using the ansi standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths less than 24 inches on regular fr-4 material is shown in figure 61 . figure 62 shows an example of when the trace lengths exceed 24 inches on regular fr-4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. 500 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 ?3 ?2 ?1 0 1 2 3 eye diagram: voltage (mv) time (ns) 14 12 10 8 6 4 2 0 ?40 ?20 0 20 40 tie jitter histogram (hits) time (ps) figure 61. data eye for lvds outputs in ansi mode with trace lengths less than 24 inches on standard fr-4, ad9230-250
ad9230 rev. 0 | page 24 of 32 600 ?600 ?400 ?200 0 200 400 ?3 ?2 ?1 0 1 2 3 eye diagram: voltage (mv) time (ns) 12 10 8 6 4 2 0 ?100 0 100 tie jitter histogram (hits) time (ps) figure 62. data eye for lvds outputs in ansi mode with trace lengths greater than 24 inches on standard fr-4, ad9230-250 the format of the output data is offset binary by default. an example of the output coding format can be found in table 12 . if it is desired to change the output data format to twos comple- ment, see the ad9230 configuration using the spi section. an output clock signal is provided to assist in capturing data from the ad9230. the dco is used to clock the output data and is equal to the sampling clock (clk) rate. in single data rate mode (sdr), data is clocked out of the ad9230 and must be captured on the rising edge of the dco. in double data rate mode (ddr), data is clocked out of the ad9230 and must be captured on the rising and falling edges of the dco see the timing diagrams shown in figure 2 and figure 3 for more information. output data rate and pinout configuration the output data of the ad9230 can be configured to drive 12 pairs of lvds outputs at the same rate as the input clock signal (single data rate, or sdr, mode), or six pairs of lvds outputs at 2 the rate of the input clock signal (double data rate, or ddr, mode). sdr is the default mode; the device may be reconfigured for ddr by setting bit 3 in register 14 (see table 13 ). out-of-range (or) an out-of-range condition exists when the analog input voltage is beyond the input range of the adc. or is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. thus, or has the same pipeline latency as the digital data. or is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in figure 63 . or remains high until the analog input returns to within the input range and another conversion is completed. by logically and-ing or with the msb and its complement, over- range high or underrange low conditions can be detected. 1 0 0 0 0 1 o r data outputs or +fs ? 1 lsb +fs ? 1/2 lsb +fs ?fs ?fs + 1/2 lsb ?fs ? 1/2 lsb 1111 1111 1111 0000 0000 0000 1111 1111 1111 0000 0000 0000 1111 1111 1110 0001 0000 0000 06002-062 figure 63. or relation to input voltage and output data timing the ad9230 provides latched data outputs with a pipeline delay of seven clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9230. these transients can degrade the converters dynamic performance. the ad9230 also provides data clock output (dco) intended for capturing the data in an external register. the data outputs are valid on the rising edge of dco. the lowest typical conversion rate of the ad9230 is 40 msps. at clock rates below 1 msps, the ad9230 assumes the standby mode. rbias the ad9230 requires the user to place a 10 k resistor between the rbias pin and ground. this resister should have a 1% tolerance and is used to set the master current reference of the adc core. ad9230 configuration using the spi the ad9230 spi allows the user to configure the converter for specific functions or operations through a structured register space inside the adc. this gives the user added flexibility to customize device operation depending on the application. addresses are accessed (programmed or readback) serially in one-byte words. each byte may be further divided down into fields, which are documented in the memory map section. there are three pins that define the serial port interface or spi to this particular adc. they are the spi sclk/dfs, spi sdio/dcs, and csb pins. the sclk/dfs (serial clock) is used to synchronize the read and write data presented the adc. the sdio/dcs (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb is an active low control that enables or disables the read and write cycles (see table 9 ).
ad9230 rev. 0 | page 25 of 32 hardware interface table 9. serial port pins mnemonic function the pins described in table 9 comprise the physical interface between the users programming device and the serial port of the ad9230. all serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value of 10 k). sclk (serial clock) is the serial shift clock in. sclk is used to synchronize serial interface reads and writes. sclk sdio (serial data input/ output) is a dual-purpose pin. the typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame. sdio this interface is flexible enough to be controlled by either proms or pic mirocontrollers as well. this provides the user with an alternate method to program the adc other than a spi controller. csb (chip select bar) is active low controls that gates the read and write cycles. csb master device reset. when asserted, device assumes default settings. active low. reset if the user chooses not to use the spi interface, some pins serve a dual function and are associated with a specific function when strapped externally to avdd or ground during device power on. the configuration without the spi section describes the strappable functions supported on the ad9230. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 64 and table 11 . configuration without the spi during an instruction phase, a 16-bit instruction is transmitted. data then follows the instruction phase and is determined by the w0 and w1 bits, which is 1 or more bytes of data. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether this is a read or write command. this allows the serial data input/output (sdio) pin to change direction from an input to an output. in applications that do not interface to the spi control registers, the spi sdio/dcs and spi sclk/dfs pins can alternately serve as standalone cmos-compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer. in this mode, the spi csb chip select should be connected to ground, which disables the serial port interface. table 10. mode selection mnemonic data may be sent in msb or in lsb first mode. msb first is default on power-up and can be changed by changing the configuration register. for more information about this feature and others, see interfacing to high speed adcs via spi at www.analog.com . external voltage configuration avdd duty cycle stabilizer enabled spi sdio/dcs agnd duty cycle stabilizer disabled avdd twos complement enabled spi sclk/dfs agnd offset binary enabled don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 0 6002-063 figure 64. serial port interface timing diagram
ad9230 rev. 0 | page 26 of 32 table 11. serial timing definitions parameter timing (minimum, ns) description t ds 5 setup time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 setup time between csb and sclk t h 2 hold time between csb and sclk t hi 16 minimum period that sclk should be in a logic high state t lo 16 minimum period that sclk should be in a logic low state t en_sdio 1 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 64 ) t dis_sdio 5 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 64 ) table 12. output data format input (v) condition (v) offset binary output mode d11 to d0 twos complement mode d11 to d0 gray code mode (spi accessible) d11 to d0 or vin+ ? vin? < 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 vin+ ? vin? = 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 vin+ ? vin? = 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 vin+ ? vin? = 0.62 1111 1111 1111 1111 1111 1111 0000 0000 0000 0 vin+ ? vin? > 0.62 + 0.5 lsb 1111 1111 1111 1111 1111 1111 0000 0000 0000 1
ad9230 rev. 0 | page 27 of 32 memory map reading the memory map table each row in the memory map table has eight address locations. the memory map is roughly divided into three sections: chip configuration register map (address 0x00 to address 0x02), transfer register map (address 0xff), and program register map (address 0x08 to address 0x2a). the addr. (hex) column of the memory map indicates the register address in hexadecimal, and the default value (hex) column shows the default hexadecimal value that is already written into the register the bit 7 (msb) column is the start of the default hexadecimal value given. for example, hexadecimal address 0x09, clock, has a hexa decimal default value of 0x01. this means bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. the default value enables the duty cycle stabilizer. overwriting this default so that bit 0 = 0 disables the duty cycle stabilizer. for more information on this and other functions, consult the interfacing to high-speed adcs via spi? user manual at www.analog.com . reserved locations undefined memory locations should not be written to other than their default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. default values coming out of reset, critical registers are preloaded with default values. these values are indicated in table 13. other registers do not have default values and retain the previous value when exiting reset. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. table 13. memory map register addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 00 chip_port_config 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles should be mirrored by the user so that lsb or msb first mode registers correctly, regardless of shift mode. 01 chip_id 8-bit chip id, bits[7:0] ad9230 = 0x0c read- only default is unique chip id, different for each device. this is a read- only register. 02 chip_grade 0 0 0 speed grade: 00 = 250 msps 01 = 210 msps 10 = 170 msps x x x read- only child id used to differentiate graded devices. transfer register ff device_update 0 0 0 0 0 0 0 sw transfer 0x00 synchronously transfers data from the master shift register to the slave.
ad9230 rev. 0 | page 28 of 32 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex) default notes/ comments adc functions 08 modes 0 0 pdwn: 0 = full (default) 1 = standby 0 0 internal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = normal (power-up) note: external pdwn pin overrides this setting. 0x00 determines various generic modes of chip operation. 09 clock 0 0 0 0 0 0 0 duty cycle stabilizer: 0 = disabled 1 = enabled (default) 0x01 od test_io reset pn23 gen: 1 = on 0 = off (default) reset pn9 gen: 1 = on 0 = off (default) output test mode: 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checker board output 0101 = pn 23 sequence 0110 = pn 9 0111 = one/zero word toggle 1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused (format determined by output_mode) 0x00 when set, the test data is placed on the output pins in place of normal data. of ain_config 0 0 0 0 0 analog input disable: 1 = on 0 = off (default) cml enable: 1 = on 0 = off (default) 0 0x00 14 output_mode 0 0 output enable: 0 = enable (default) 1 = disable ddr: 1 = enabled 0 = disabled (default) output invert: 1 = on 0 = off (default) data format select: 00 = offset binary (default) 01 = twos complement 10 = gray code 0x00 0 15 output_adjust 0 0 lvds course adjust: 0 = 3.5 ma (default) 1 = 2.0 ma lvds fine adjust: 001 = 3.50 ma 010 = 3.25 ma 011 = 3.00 ma 100 = 2.75 ma 101 = 2.50 ma 110 = 2.25 ma 111 = 2.00 ma 0x00 0 16 output_phase output clock polarity 1 = inverted 0 = normal (default) 0 0 0 0x03
ad9230 rev. 0 | page 29 of 32 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex) default notes/ comments 17 flex_output_delay output delay enable: 0 = enable 1 = disable output clock delay: 00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns 0 18 flex_vref input voltage range setting: 10000 = 0.98 v 10001 =1.00 v 10010 = 1.02 v 10011 =1.04 v 11111 = 1.23 v 00000 = 1.25 v 00001 = 1.27 v 01110 = 1.48 v 01111 = 1.50 v 0 2a ovr_config or position (ddr mode only): 0 = pin 9, pin 10 1 = pin 21, pin 22 or enable: 1 = on (default) 0 = off 00000001
ad9230 rev. 0 | page 30 of 32 outline dimensions compliant to jedec standards mo-220-vlld-2 112805-0 pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 4.45 4.30 sq 4.15 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0 .85 0 .80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.30 min exposed pad (bottom view) figure 65. 56-lead lead frame chip scale package [lfcsp_vq] 8 mm 8 mm body, very thin quad (cp-56-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad9230bcpz-170 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-2 1 ad9230bcpz-210 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-2 1 ad9230bcpz-250 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-2 1 ad9230-170ebz lvds evaluation board with ad9230bcpz-170 1 ad9230-210ebz lvds evaluation board with ad9230bcpz-210 1 ad9230-250ebz lvds evaluation board with ad9230bcpz-250 1 1 z = pb-free part.
ad9230 rev. 0 | page 31 of 32 notes
ad9230 rev. 0 | page 32 of 32 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06002-0-2/07(0)

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